Gate Oxide Breakdown

The gate oxide thickness, (tox), of Complementary Metal Oxide Semiconductor (CMOS) processes has been steadily been thinning as a result of technology trends. To keep the switching power dissipation of integrated circuits at bay, successive technology generations have relied on reducing the supply voltage. In order to maintain performance, and control short channel effects, however, a reduction in the transistor oxide thickness is required to provide sufficient current drive at the reduced supply voltages. At the 70nm technology node, CMOS processes will have oxide thicknesses of 1.2nm to 1.6nm [1]. Since electric fields in the gate oxide are expected to rise with scaling, the long-term reliability of thin oxides becomes an important concern in modern, deep-submicron (< 0.10μm) processes. In this paper the causes, symptoms, and failure models of gateoxide breakdown will be presented. Section 2 provides some relevant background. Section 3 explains what gate-oxide breakdown is and what are its causes. Section 4 explains some of the effects of gateoxide breakdown in both transistors and circuits. In Section 5 different failure models for gate-oxide breakdown are presented. Section 6 goes over the statistics of gateoxide breakdown in recent technologies. In Section 7 the use of CAD tools to predict gate-oxide breakdown will be explored, and in Section 8 design styles that reduce the probability of gate-oxide breakdown will be presented. Finally Section 9 concludes.